Detailed Microcontroller Architecture Based on a Hardware Scheduler Engine and Independent Pipeline Registers
Abstract
In the world of real time operating systems, task switching, communication between threads and synchronization are implemented in software. Some of the mechanisms used may introduce big latencies in task recurrence, task jitter. This kind of problem, which is sporadic, may lead to system failure for safety-critical areas. This issue may occur in the real time systems that have really fast response time as requirements. For this particular example, the tasks are succeeding very fast, resulting in a lot of overhead because of the time spent in task switch. Our research has led us to the conclusion that a microcontroller architecture, based on a static hardware Scheduler and independent Pipeline Registers, will be capable of executing multiple tasks with approximately no delay between every task switch (5 machine cycles). The nMPRA (n Multi-Purpose Register Architecture) architecture, which consists of 2 sets of registers: local such as coprocessor 2 and global such as a peripheral on the slow bus, offers support for preemptive real time operating systems. Both architectures, nMPRA and nHSE (n Hardware Scheduler Engine), complement each other and take the real time operating system programming to a whole new level.
References
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